Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
The flexibility and computing power offered by modern PLDs has lead to increased usage of these devices in a variety of different systems. For example, PLDs are used extensively in networking and communication related systems. Increasingly, these sorts of systems, as well as others, are implemented using circuits that rely upon dynamic random access memory (DRAM). Accordingly, these systems need memory controllers to facilitate communication between the various system components and the DRAM(s). A memory controller, in general, refers to a system (or a subsystem) that includes circuitry that can read data from DRAM, write data to DRAM, refresh DRAM to avoid loss of data, as well as perform other administrative functions that may be required to communicate with the DRAM.